This invention relates to the field of integrated circuits (ICs), and more specifically to IC packages.
Integrated circuit (IC) devices typically include an IC chip that is housed in a xe2x80x9cpackagexe2x80x9d that typically includes a plastic, ceramic or metal substrate. The IC chip includes an integrated circuit formed on a thin wafer of silicon. The IC package supports and protects the IC chip and provides electrical connections between the integrated circuit and an external circuit or system.
There are several IC package types, including ball grid arrays (BGAs), pin grid arrays (PGAs), plastic leaded chip carriers, and plastic quad flat packs. Each of the IC package types is typically available in numerous sizes. The IC package type selected by an IC manufacturer for a particular IC chip is typically determined by the size/complexity of the IC chip (i.e., the number of input/output terminals), and also in accordance with a customer""s requirements.
FIGS. 1 and 2 show bottom and side sectional views of a typical BGA IC device 100 including an IC chip 110 mounted on an upper surface 122 of a BGA IC package 120. BGA IC package 120 includes a non-conductive (e.g., plastic or ceramic) package substrate 121 having an upper surface 122 on which is formed contact pads 125, sixty-four solder balls (sometimes referred to as solder bumps) 126 extending from a lower surface 127 of the substrate 121, and conductive vias 128 extending through package substrate 121 to electrically connect contact pads 125 and solder balls 126. The sixty-four solder balls 126 are arranged in a square xe2x80x9cfootprintxe2x80x9d (pattern) simplify the following descriptionxe2x80x94typical BGA IC packages include several hundred solder balls that are arranged in square or rectangular footprints. Bond wires 130 provide electrical connections between bonding pads 115 of IC chip 110 and conductive contact pads 125 formed on package substrate 120, thereby providing electrical signal paths between solder balls 126 and IC chip 110. For example, a signal applied to solder ball 126-A travels along via 128-A to contact pad 125-A, and from contact pad 125-A along bond wire 130-A to bonding pad 115-A of IC chip 110. An optional cover 129, such as a cap, mold compound, or xe2x80x9cglob topxe2x80x9d, is placed or formed over IC chip 110 and bond wires 130 for protection.
IC manufacturers typically test their IC devices thoroughly before shipping to customers. Part of this IC testing determines if the IC device is functional, and the results of these tests provide customers operating characteristics that are used by the customers in designing their systems. Another portion of the testing process involves determining the reliability of the packaged IC device when subjected to various environmental conditions. Reliability testing can be divided into two levels. During first level reliability testing, packaged ICs are subjected to extreme temperatures, moisture, and mechanical stress (e.g., shock) to determine the maximum environmental conditions in which the packaged.IC device can reliably operate. During second level reliability testing, packaged ICs are subjected to various temperature, moisture, and mechanical stress (e.g., shock) cycles to determine the life expectancy between the IC device and a printed circuit board under such conditions. The statistical data generated during first and second level reliability testing is then provided to customers to help customers improve the reliability of their systems.
FIGS. 3(A) through 3(C) illustrate one part of second level reliability testing that involves testing for solder joint fractures between BGA IC device 100 and a printed circuit board (PCB) 150.
FIG. 3(A) shows BGA IC device 100 mounted on PCB 150 before thermal cycling. BGA IC device 100 is mounted on a PCB 150 using well-known methods such that solder balls 126 are partially melted to form a solder joint between solder balls 126 and conductive traces 155 provided on PCB 150.
FIG. 3(B) shows BGA IC device 100 and PCB 150 after thermal cycling is performed. It is well established that packaged IC devices and PCBs expand and contract at different rates in response to thermal cycling. FIG. 3(B) illustrates that an expansion rate A exhibited by packaged IC device 100 along a plane parallel to package substrate 121 is different from an expansion rate B exhibited by PCB 150, thereby generating stresses in the solder joints that can produce fractures 160. These fractures can significantly increase board-to-device resistances, and in some cases can produce open circuits between BGA IC device 100 and PCs 150. Second level reliability testing is utilized to determine when these fractures first occur (e.g., the minimum number of thermal cycles). This information is typically used by customers in the selection of a package type that is best suited for their particular system.
It is also established that packaged IC devices have a tendency to warp in response to thermal cycling. Referring to FIG. 1, package substrate 121 is divided into five regions R1 through R5, with region R5 being located in a center of package substrate 121. The tendency to warp is greatest in corner regions R1 through R4, and least in central region R5. As depicted in a simplified manner in FIG. 3(C), the warping force (indicated by curved arrows C) generates a torque that, when combined with the solder joint fracture problem described above, greatly increases the likelihood of disconnection between solder balls 126 and conductive traces 155.
As suggested above, second level reliability is statistical in nature, and data related to the number of thermal cycles needed to produce solder joint fractures is most accurate when a large number of samples are tested. However, such testing using conventional methods is highly time consuming and, when performed on a large number of BGA IC devices 100, can be very expensive. Therefore, what is needed is an efficient and low-cost method and assembly for determining when solder fracture occurs in a particular BGA package.
As also suggested above, warping of a BGA package can produce catastrophic system failures. What is also needed is an efficient method and assembly for identifying flaws or weaknesses in a BGA package design so that corrective measures can be taken to prevent the warping of a particular type of BGA package due to thermal cycling.
The present invention is directed to an efficient and low-cost method and assembly for detecting solder joint fractures that can be used to identifying flaws or weaknesses in a BGA package design.
In accordance with a first embodiment of the present invention, an assembly for analyzing solder joint fractures in response to thermal cycling includes an IC package mounted (i.e., soldered) to a test PCB. The IC package includes solder balls extending from a lower surface thereof that are arranged in a footprint (pattern) and are connected by conductive vias extending through the package body to contact pads formed on an upper surface thereof. Instead of being wire bonded to an IC chip, selected pairs of these contact pads are connected together to form a first daisy chain portion. The test PCB is provided with contact pads, which are arranged to match the IC package footprint. Similar to the IC package, associated pairs of the contact pads are connected by conductive lines to form a second daisy chain portion. The daisy chain is completed when the IC package is mounted on the test PCB and the solder balls are soldered to the contact pads. By alternating between the test PCB contact pads that are linked by conductive traces and the solder balls that are linked within the package, the daisy chain provides a conductive path between a first test pad and a final pad that passes through all solder balls of the IC package. During testing, a voltage is applied to the first test pad (i.e., a first end of the daisy chain) and current is measured at the final test pad (i.e., a second end of the daisy chain). The PCB and IC package are then subjected to thermal cycling and repeatedly tested until a solder joint fracture (i.e., an open circuit) is detected. By counting the number of thermal cycles required to produce the solder joint fracture, accurate expected lifetime data is generated for the IC package that can be used by a customer in the design of the customer""s system.
In accordance with an aspect of the present invention, intermediate test pads are provided on the test PCB and connected to intermediate points of the daisy chain to facilitate identifying the region of the IC package footprint in which a solder joint fracture occurs during thermal cycling. The conductive path, which is formed by the daisy chained solder balls and contact pads, is routed through predetermined regions of the IC package footprint in a serial manner. For example, the conductive path segment travels through all solder balls located in one corner of a square IC package footprint before linking with a second segment passing through another region of the footprint. By providing an intermediate test pad at each end of the conductive path segments, each region of the footprint can be tested for electrical open circuits, thereby facilitating identification of the region in which solder joint fractures occur. Accordingly, package design defects to be quickly and efficiently corrected when test data indicates that a statistically large number of solder joint fractures occur in a particular footprint region.
In accordance with another aspect of the present invention, multiple test sites are provided on a test PCB, each test site including contact pads for mounting one IC package. Each test site is connected by elongated conductive traces to a test socket that can be received in a testing device. In particular, one terminal of the test socket is connected to a first contact pad of each test site, and is used to transmit a test voltage to each test site. A second contact pad of each test site is connected by a conductive tract to a corresponding second terminal of the test socket, thereby allowing simultaneous testing of several IC packages using a single test PCB.
In accordance with a second embodiment of the present invention, an assembly for analyzing solder joint fractures in response to thermal cycling includes a xe2x80x9cflip-chipxe2x80x9d IC package mounted (i.e., soldered) to a test PCB. The xe2x80x9cflip-chipxe2x80x9d IC package includes solder balls extending from a lower surface thereof that are arranged in a footprint (pattern) surrounding a central cavity formed on the lower surface, and are connected by conductive vias extending through the package body to contact pads located in the central cavity. A dummy IC (substrate) is mounted in the central cavity such that solder balls located on the dummy substrate are connected to the contact pads located in the central cavity. The dummy substrate is provided with metal lines connecting selected pairs of these solder balls, which in turn connect together selected pairs of contact pads to form a first daisy chain portion. As in the first embodiment, the test PCB is provided with contact pads, which are arranged to match the IC package footprint and to form a second daisy chain portion.